The present invention relates to semiconductor devices and, in particular, relates to a semiconductor device and a method of manufacturing the same, in which a wiring layer circuit is provided for a multilayered wiring layer.
In a typical semiconductor device, a logic circuit part, which includes an active element such as a transistor, is formed over a semiconductor substrate, and plural wiring layers are formed over this logic circuit part. In such a semiconductor device, a desired function thereof is achieved by the logic circuit part.
However, there is a case in which another function is desired to be added although a basic function of the logic circuit part is not changed. In such a case, it is a problem from a point of cost to newly perform layout design. If a difference between these functions is absorbed by means of providing another additional circuit part without changing the logic circuit over the semiconductor substrate as far as possible, it is effective in terms of cost. A technique which responds to such a requirement is disclosed in Japanese Patent Laid-Open No. 2010-141230 (Patent Document 1).
Patent Document 1 discloses a technique which provides a semiconductor layer in a wiring layer and forms a semiconductor element using the semiconductor layer. Examples of material for the semiconductor layer are an oxide semiconductor such as InGaZnO (IGZO) and ZnO, poly-silicon, and amorphous silicon. The semiconductor element provided in the wiring layer is used as a transistor of a switching element, for example. Further, there is also disclosed a technique in which the semiconductor element is provided with a trap film and a back-gate electrode to be used as a memory element.
The technique of forming an active wiring element in an LSI multi-layer wiring utilizing the oxide semiconductor has been studied, and a basic structure of the active element is known from the above Patent Document 1. Further, basic action such as transistor action and diode action has been confirmed. For forming a logic circuit or the like using the active element in the multi-layered wiring layer, it is necessary to form an inverter element.
The active wiring element described in Patent Document 1 is an n-type transistor which can be formed in the wiring layer. An oxide semiconductor layer is used as a conduction channel, a lower layer of the conduction channel is used as a gate insulating film, and a contact from an upper layer to the oxide semiconductor layer is used as a source/drain (S/D) contact.
For the active wiring element of Patent Document 1, however, action of a single transistor is described, but an inverter structure which can be formed in the multi-layered wiring layer is not described, and thus it is not clear how to form an oscillation circuit or a logic circuit which can be formed in the multi-layered wiring layer.
Further, the influence of characteristic variation (against temperature and within a surface) is large in a transistor manufactured as described above. For a single transistor, it is known that a temperature dependence provides a large characteristic variation within a wafer, and, when an inverter element is formed by the use of a transistor and a resistance element (foundation transistor resistance, wiring resistance, or external resistance), sometimes variation is caused in an oscillation frequency and an output voltage because of the influence from the characteristic variation of the transistor.
Moreover, it is necessary to forma load resistance having a high resistance value in an area-saving manner. When a diffusion layer of a foundation layer, in which a logic circuit is formed, or the wiring layer is used for a load resistance, resistivity thereof is low and therefore there arises a problem that a large area is necessary for forming the load resistance having a high resistance value.